Current-parking switching regulator upstream controller

ABSTRACT

A system and method are provided for regulating a voltage at a load. A current source is configured to provide a current to a voltage control mechanism and the voltage control mechanism is configured to provide a portion of the current to the load. The current is generated based on the portion of the current that is provided to the load. A system includes the current source, an upstream controller, and the voltage control mechanism that is coupled to the load. The upstream controller is coupled to the current source and is configured to control a current that is generated by the current source based on a portion of the current that is provided to the load.

FIELD OF THE INVENTION

The present invention relates to regulator circuits.

BACKGROUND

Conventional devices such as microprocessors and graphics processors that are used in high-performance digital systems may have varying current demands based on the processing workload. For example, current demands may increase dramatically when a block of logic is restarted after a stall or when a new request initiates a large computation such as the generation of a new image. Conversely, current demands may decrease dramatically when a block of logic becomes idle. When the current demand increases and sufficient power is not available, the supply voltage that is provided to the device may drop below a critical voltage level, potentially causing the device to fail to function properly. When the current demand decreases and the supply voltage that is provided to the device rises above a critical voltage level, circuits within the device may fail to function properly and may even be destroyed.

A conventional multi-phase switching regulator is an electric power conversion device that interfaces between a power supply and a device, providing current to the device and responding to changes in current demands to maintain a supply voltage level. However, a conventional multi-phase switching regulator relies on a large inductor for voltage conversion and the large inductor limits the ability of the conventional multi-phase switching regulator to quickly respond to dramatic changes in current demands (i.e., current transients). A typical 30 A phase of the conventional multi-phase switching regulator may use a 0.5 μH inductor for voltage conversion. The current response is limited to di/dt=V/L which for V=11 V (dropping a 12V input to a 1 V supply voltage level) and L=0.5 μH gives 22 A/μs. Increasing the current provided to a device by 10 A in would require at least 500 ns. Additionally, synchronization of the pulse width modulation switching operation may increase the current response time of the conventional multi-phase switching regulator by several microseconds. When a clock period of the device is less than the current response time, the device may fail to function properly. A 500 MHz clock has a period of 2 ns, so hundreds of clock periods may occur during a 500 ns current response time.

Thus, there is a need for improving regulation of voltage levels and/or other issues associated with the prior art.

SUMMARY

A system and method are provided for regulating a voltage at a load. A current source is configured to provide a current to a voltage control mechanism and the voltage control mechanism is configured to provide a portion of the current to the load. The current is generated based on the portion of the current that is provided to the load. A system includes the current source, an upstream controller, and the voltage control mechanism that is coupled to the load. The upstream controller is coupled to the current source and is configured to control a current that is generated by the current source based on a portion of the current that is provided to the load.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A illustrates an electric power conversion system including an electric power conversion device that is implemented as a current-parking switching regulator with a single inductor, in accordance with one embodiment;

FIG. 1B illustrates a multi-phase switching regulator that includes multiple electric power conversion devices, in accordance with one embodiment;

FIG. 1C illustrates a current-parking switching regulator with a split inductor, in accordance with one embodiment;

FIG. 2 illustrates a flowchart of a method for regulating the voltage level provided to a load, in accordance with one embodiment;

FIG. 3A illustrates a current-parking switching regulator, in accordance with one embodiment;

FIG. 3B illustrates waveforms controlling the portion of current that is provided to the load of the current-parking switching regulator shown in FIG. 3A, in accordance with one embodiment;

FIG. 3C illustrates a duty factor measurement unit of an upstream controller, in accordance with one embodiment;

FIG. 3D illustrates another duty factor measurement unit of an upstream controller, in accordance with one embodiment;

FIG. 4A illustrates an upstream controller of the current-parking switching regulator shown in FIG. 3A, in accordance with one embodiment;

FIG. 4B illustrates another upstream controller of the current-parking switching regulator shown in FIG. 3A, in accordance with one embodiment;

FIG. 4C illustrates a flowchart of a method for an upstream controller to control the current generated by a current control mechanism, in accordance with one embodiment;

FIG. 5A illustrates another flowchart of a method for regulating the voltage level provided to a load, in accordance with one embodiment;

FIG. 5B illustrates a system including a current-parking switching regulator driving two loads using a shared current source, according to one embodiment;

FIG. 5C illustrates a diagram of the current-parking switching regulator within a system, according to one embodiment;

FIG. 6A illustrates waveforms generated by a current-parking switching regulator, in accordance with one embodiment;

FIG. 6B illustrates an enlarged view of a portion of the waveforms shown in FIG. 6A, in accordance with one embodiment;

FIG. 6C illustrates another enlarged view of a portion of the waveforms shown in FIG. 6A, in accordance with one embodiment; and

FIG. 7 illustrates an exemplary system in which the various architecture and/or functionality of the various previous embodiments may be implemented.

DETAILED DESCRIPTION

An electric power conversion device provides a desired output voltage level to a load, such as a device. The electric power conversion device converts power received from a power source (e.g., battery or main power supply) to a supply voltage level that is provided to the load. An inductor is used to deliver additional current to the load and regulate the output voltage level with switching mechanisms modulating the average current that flows through the inductor. A capacitor is coupled between the load and ground to store any excess current (difference between the current provided through the inductor and the current delivered to the load).

FIG. 1A illustrates an electric power conversion system 100 including an electric power conversion device 120 that is implemented as a current-parking switching regulator with a single inductor L1, in accordance with one embodiment. The electric power conversion device 120 may be one phase of a multi-phase switching regulator, as shown in FIG. 1B. The electric power conversion device 120 is configured to provide a desired output voltage level (V_(L)) at the load 110 by converting power received from an electric power source 108. The electric power conversion device 120 includes a current control mechanism and a voltage control mechanism. The current control mechanism is coupled to the electric power source 108 and the controller 105 and is operable to control the average of the current I_(L1) flowing through the inductor L1 and ensure a minimum current is provided across the multiple phases of a multi-phase switching regulator. For example, as illustrated, the current control mechanism may include one or more first switching mechanisms M1 and one or more second switching mechanisms M2. The switching mechanisms M1 and M2 may each include, for example, N-type power MOSFETs (metal oxide semiconductor field-effect transistor), and/or other switching mechanisms. Although single switching mechanisms M1 and M2 is illustrated for the ease of understanding, it will be appreciated that a plurality of switching mechanisms M1 and M2 may be connected in parallel to increase current capacity, decrease conduction losses, and the like.

The controller 105 is configured to apply one or more control signals to the switching mechanisms M1 and M2. For example, the controller 105 may be configured to generate pulse width modulation (PWM) signals or pulse frequency modulation (PFM) signals, a combination of PWM and PFM, and/or different control signals to selectively enable the switching mechanisms M1 and M2 according to a duty factor. Regardless of the specific configuration, the controller 105 is configured to provide control signals such that the switching mechanisms M1 and M2 are not concurrently enabled (i.e., turned on). In other words, only one of switching mechanism M1 and M2 is enabled at a time. Enabling switching mechanisms M1 and M2 concurrently provides a direct path between the supply of electric power source 108 and ground, thereby potentially damaging the electric power conversion device 120 and/or the load 110 and/or resulting in undesirable high power usage.

In contrast with conventional electric power conversion devices, the electric power conversion device 120 includes the voltage control mechanism in addition to the current control mechanism. The voltage control mechanism is coupled between the current control mechanism (at the downstream end of the inductor L1) and the load 110 and is operable to control the V_(L). The current control mechanism is configured to generate current I_(L1) that is “parked” in the inductor L1. The voltage control mechanism is operable to control the amount of the inductor current I_(L1) that is delivered to a capacitor C1. As such, the voltage control mechanism comprises one or more switching mechanisms M3 and one or more switching mechanisms M4. The switching mechanisms M3 and M4 may each include, for example, N-type planar MOSFETs (metal oxide semiconductor field-effect transistor), and/or other switching mechanisms. Although single switching mechanisms M3 and M4 are illustrated for the ease of understanding, it will be appreciated that a plurality of switching mechanisms M3 and M4 may be connected in parallel to increase current capacity, decrease conduction losses, and the like.

A conventional electric power conversion device does not include the switching mechanisms M3 and M4, so the inductor L1 would instead be coupled directly to the capacitor C1 and the load 110. Any excess current that flows through the inductor L1 and is not consumed by the load 110 is accumulated on the capacitor C1 and any current drawn by the load 110 that exceeds the current provided by the inductor L1 is sourced by the capacitor C1. The inductor L1 resists changes in current, thereby preventing the stored energy in the inductor L1 from being released all at once to the load 110 when the current demands of the load 110 increase. This property of inductors, along with the storage capacity of the capacitor C1 enable V_(L) to be sufficiently stable during steady-state operation (i.e., when the current demand of the load 110 is relatively constant). Nonetheless, there is some “ripple” in V_(L) that depends on the size of the inductor L1, the size of the capacitor C1, and/or the switching frequency of the controller 105, among other factors. Generally speaking, as the size of the inductor L1 increases, the output ripple during steady state operation (i.e., approximately constant current demand at the load 110) proportionally decreases. Accordingly, the inductor L1 may be sized large enough in order to provide a V_(L) that does not fluctuate outside a desired supply voltage range for the load 110. However, as previously explained, a conventional electric power conversion device is typically unable to respond to changes in the current needs of the load 110 quickly enough. The large inductance of L1 that is needed to reduce the ripple at V_(L) increases the response time, producing larger voltage deviations when the current demand of the load 110 varies. The voltage control mechanism that is included in the electric power conversion device 120 enables faster response time to changes in current demand of the load 110 without necessitating decreasing the size of the inductor L1 which may cause the voltage ripple at V_(L) to increase.

In contrast to the switching mechanisms M1 and M2, the voltage across the switching mechanisms M3 and M4 may be substantially less than the voltage drop across the inductor L1. For example, the voltage supplied at the downstream of the inductor L1 may be substantially equivalent to the output voltage at the load 110. Because the switching mechanisms M3 and M4 are switching a lower voltage, the switching mechanisms M3 and M4 may be constructed from lower-voltage devices, such as “planar” MOS transistors, as compared to the switching mechanisms M1 and M2. Lower-voltage devices can typically be switched at higher frequencies compared with higher-voltage devices, such as power MOSFETs. Therefore, power loss due to switching is reduced for the switching mechanisms M3 and M4 compared with the switching mechanisms M1 and M2. Hence switching mechanisms M3 and M4 can be switched at a substantially higher frequency than switching mechanisms M1 and M2.

Switching mechanisms M3 and M4 may be incorporated into an integrated circuit, thereby potentially reducing space used and/or reducing cost compared with using discrete components. For example, the switching mechanisms M3 and M4 may be realized on the same integrated circuit as the load 110, may be integrated on a separate die on the same package as the load 110, or may be integrated on a separate package. The switching mechanisms M3 and M4 may be realized as standard-voltage “core” transistors in a typical digital integrated-circuit process, or the switching mechanisms M3 and M4 may be realized as higher-voltage thick-oxide input-output transistors in a typical integrated-circuit process. In a preferred embodiment, the switching mechanism M4 is a P-type planar MOSFET and the switching mechanism M3 is an N-type planar MOSFET. However, one of ordinary skill in the art will understand that either type of MOSFET may be used for either switching mechanism with appropriate gate-drive circuitry without departing from the scope of the present disclosure.

The controller 105 may be further configured to apply one or more control signals to the voltage control mechanism. For example, the controller 105 may be configured to provide control signals to the switching mechanisms M3 and M4. As with the control signals provided to the switching mechanisms M1 and M2, the control signals that are provided to the switching mechanisms M3 and M4 may utilize PWM, PFM, bang-bang control, and/or any other suitable control schema in order to selectively enable the switching mechanism M3 or the switching mechanism M4. In some embodiments the control signals coupled to the switching mechanisms M3 and M4 may be at least partially synchronous with the control signals coupled to the switching mechanisms M1 and M2. In other embodiments, the control signals coupled to the switching mechanisms M3 and M4 may be asynchronous with the control signals coupled to the switching mechanisms M1 and M2. Furthermore, the control signals coupled to the switching mechanisms M3 and M4 may be provided at a different frequency than the control signals that are coupled to the switching mechanisms M1 and M2.

Regardless of the specific configuration of the control signals that are coupled to the switching mechanisms M3 and M4, the controller 105 may be configured to selectively enable the switching mechanism M3 and disable the switching mechanism M4 to disable the flow of current I_(L1) to the load 110. Specifically, by enabling the switching mechanism M3 and disabling the switching mechanism M4, the instantaneous inductor current I_(L1) flowing through the inductor L1 is diverted through the switching mechanism M3 to ground instead of being delivered to the capacitor C1. Conversely, by enabling the switching mechanism M4 and disabling the switching mechanism M3, substantially all of the instantaneous inductor current I_(L1) flowing through the inductor L1 (less transistor conduction losses, inductor winding resistance, and the like) is provided to the capacitor C1.

The controller 105 may use PWM or PFM to switch the voltage control mechanism or may use a bang-bang technique. In either case, the duty factor (DF) determines the portion of the inductor current I_(L1) that on average is supplied to the capacitor C1. The duty factor may range from 0-100%, where 0% corresponds to the state where the switching mechanism M4 is disabled (i.e., turned off) and the switching mechanism M3 is enabled and a 100% corresponds to the state where the switching mechanism M4 is enabled and the switching mechanism M3 is disabled. Changing the duty factor thereby changes the charge/discharge timing of the capacitor C1—a higher duty factor increases the current flow to the capacitor C1 and the load 110.

The capacitor C1 smoothes the square wave supply current provided through the switching mechanism M4 to generate I_(Load) that is provided to the load 110. The I_(Load) is provided to the load 110 according to the duty factor and the inductor current I_(L1), as follows: I_(Load)=DF×I_(L1). As with the switching mechanisms M1 and M2, control signals are provided to the switching mechanisms M3 and M4 such that the switching mechanisms M3 and M4 are not concurrently enabled to avoid providing a direct path between the load 110 and ground (i.e., a short circuit across the capacitor C1).

During steady-state operation, the switching mechanism M3 is disabled and the switching mechanism M4 is enabled, such that substantially all of the inductor current I_(L1) is provided to the load 110 as I_(Load). The switching mechanisms M1 and M2 are selectively enabled (“switched”) in order to control the inductor current I_(L1), thereby controlling V_(L). In this manner, if the voltage provided to the load 110 (V_(L)) is constant, the current provided through the switching mechanism M4 is substantially equivalent to the inductor current I_(L1).

In sum, the current control mechanism is configured to generate current I_(L1) that is parked in the inductor L1 and metered out to the load 110 by the voltage control mechanism. Because the voltage levels applied to the switching mechanisms M3 and M4 are low (i.e., the supply voltage of the load 110), the switching mechanisms M3 and M4 may be implemented as fast, inexpensive planar transistors and can be operated at very high frequency (e.g., 300 MHz) allowing very rapid response to current transients at the load 110. When the current demand at the load 110 changes (i.e., not steady-state operation), the switching mechanisms M3 and M4 of the voltage control mechanism may be controlled to quickly respond to the change in current demand by increasing or decreasing the amount of the current I_(L1) this is metered out to the load 110. In general, the switching frequency of the current control mechanism is slower than the switching frequency of the voltage control mechanism due to the different types of switching mechanisms that are used.

A lumped element CP in the electric power conversion device 120 represents the parasitic capacitance on the downstream side of the inductor L1. Each time the switching mechanisms M3 and M4 are switched, the parasitic capacitance CP is charged to the load voltage V_(L) (when the switching mechanism M4 is enabled) and then discharged to ground (when the switching mechanism M3 is enabled). Thus, each switching cycle of the switching mechanisms M3 and M4 an energy E_(P) of E _(P)=(CP)V _(L) ² is dissipated by charging and discharging the parasitic capacitance CP.

In a typical embodiment of the electric power conversion device 120, the inductor L1 is a surface mount 0.5 uH 30 A inductor, the switching mechanisms M3 and M4 are located on the package, and the capacitor C1 is on-chip and on-package bypass capacitance. Capacitor CP includes the capacitance of the vias, board traces, and package traces between the inductor L1 and the switching mechanisms M3 and M4. In a typical application the capacitance CP may total as much as 500 pF. If CP=500 pF and V_(L)=1V, then E_(p) is 500 pJ. At a switching frequency of 300 MHz, 150 mW is dissipated charging and discharging CP. When the current control mechanism and the voltage control mechanism of the electric power conversion device 120 are configured as one of a plurality of phases of a regulator, E_(P) is scaled by the number of phases for the total energy that is dissipated due to the cumulative parasitic capacitance.

This switching power increases as the switching frequency (f_(s)) of the switching mechanisms M3 and M4 is increased. One would like to switch the switching mechanisms M3 and M4 at a high frequency to minimize the required size of C1 that is given by

$C_{1} = \frac{I_{L\; 1}\left( {1 - {DF}} \right)}{f_{S}V_{R}}$ where DF is the duty factor of the switching mechanism M4 and V_(R) is a ripple voltage of V_(L).

For example with a phase current of 30 A, a frequency of 300 MHz, and a ripple voltage of 20 mV the required capacitance C1 is 5 uF per phase. C1 is typically distributed across many smaller capacitors on the package to give low series inductance and to provide a flat impedance as a function of the switching frequency. Increasing the switching frequency reduces the required size of C1 but at the expense of increased switching power E_(P).

An advantage of a current-parking switching regulator, such as the electric power conversion device 120, is that C1 is the only filter capacitance needed. In comparison, a conventional electric power conversion device that does not include the switching mechanisms M3 and M4 relies on a large (hundreds of μF) filter capacitance to filter the low frequency (typically 300 kHz) ripple.

The configuration of the electric power source 108, the controller 105, the switching devices M1 and M2, and the inductor L1 shown in FIG. 1A is typically referred to as a “buck” converter. While the electric power conversion device 120 is described in the context of this buck converter, one of ordinary skill in the art will understand that the techniques described to regulate a voltage provided to the load 110 can be applied to other “switch-mode” power conversion circuits including, but not limited to, a forward converter, a half-bridge converter, a full-bridge converter, a flyback converter, and/or variants thereof.

FIG. 1B illustrates a multi-phase switching regulator 150 that includes electric power conversion devices 120, in accordance with one embodiment. Each of the electric power conversion devices 120 is one phase of a six-phase switching regulator. Each electric power conversion device 120 is configured to provide a desired output voltage level (V_(L)) at the load 110 by converting power received from an electric power source 108 for one phase of the six phases. A single controller may be used to control each of the electric power conversion devices 120 or each electric power conversion device 120 may include a dedicated controller 105 (as shown in FIG. 1B). A single filter capacitor C1 may be shared by the different electric power conversion devices 120 rather than including a filter capacitor C1 in each of the electric power conversion devices 120. Additionally, one or more of the electric power conversion devices 120 may be replaced with a current-parking switching regulator with a split inductor or a conventional electric power conversion device.

FIG. 1C illustrates an electric power conversion system 160 including an electric power conversion device 180 that is implemented as a current-parking switching regulator with a split inductor, in accordance with one embodiment. Compared with the electric power conversion device 120 shown in FIG. 1A, the electric power conversion device 180 includes a first inductor L11 that is coupled in series with a second inductor L2 to form a split inductor. Splitting the inductor reduces losses due to parasitic capacitance CPA on the downstream side of the first inductor L11.

The electric power conversion device 180 may be one phase of a multi-phase switching regulator. The electric power conversion device 180 is configured to provide a desired output voltage level (V_(L)) at the load 170 by converting power received from an electric power source 108. The electric power conversion device 180 includes a current control mechanism and a voltage control mechanism. The current control mechanism is coupled to the electric power source 108 and the controller 165 may be configured to generate control signals in the same manner as the controller 105 and is operable to control the average of the current I_(L11) flowing through the inductor L11 and the current I_(L2) flowing through the inductor L2. For example, as illustrated, the switching mechanisms M11 and M12 are configured and operable in the same manner as previously described switching mechanisms M1 and M2, respectively. Similarly, the switching mechanisms M13 and M14 are configured and operable in the same manner as previously described switching mechanisms M3 and M4, respectively. The capacitor C11 performs substantially the same function as the capacitor C1.

Using two different inductors L11 and L2 to form a split inductor reduces the switching energy so that the bulk of the parasitic capacitance falls between the inductor L11 and L2, shown as a first parasitic capacitance CPA. In one embodiment, L11 is a 0.5 μH 30 A first inductor on a printed circuit board (e.g., a discrete component) and the second inductor L2 is a 1 nH inductor in the package that encloses the load 170. The first parasitic capacitance CPA includes the capacitance of the vias, board traces, and package traces between the first inductor L11 and the second inductor L2. The first parasitic capacitance CPA may be approximately 490 pF. The second parasitic capacitance CPB consists primarily of the drain capacitance of the switching mechanisms M13 and M14 and may be approximately 10 pF. If CPB=10 pF and V_(L)=1V, then E_(P) is 10 pJ and, at a switching frequency of 500 MHz, 5 mW is dissipated charging and discharging CPB.

The switching frequency of 500 MHz, allows use of a 0.5 μF capacitor (implemented as a distributed array of smaller capacitors in some embodiments) for the capacitor C11. The 1 nH inductance of the second inductor L2 can be formed by integrating a ferrite bead around the traces or bumps carrying the current I_(L2) or by simply running a trace a suitable distance from the ground return (making the second inductor L2 a planar air-core inductor). The resonant frequency of the tank circuit formed by L2 and the first parasitic capacitance CPA is f_(r)=230 MHz. Thus, as long as the switching frequency of the switching mechanisms M13 and M14 is high compared to f_(r), the capacitance of the first parasitic capacitance CPA is effectively isolated from the switching node V_(L). Because the first parasitic capacitance CPA is located between the first inductor L11 and the second inductor L2, CPA is isolated and is lossless. Any excess current is stored in the split inductor formed by the first inductor L11 and the second inductor L2.

FIG. 2 illustrates a flowchart 200 of a method for regulating the voltage level provided to the load 110 or 170, in accordance with one embodiment. At step 205, a current source is configured to generate a current I_(L1) or I_(L11). At step 210, a voltage control mechanism is configured to provide a portion of the current to the load to regulate the voltage level at the load. In one embodiment, if the voltage level at the load 110 or 170 is greater than a maximum voltage level, the voltage control mechanism is switched to decouple the current source from the load 110 or 170 and to couple the current source to a current sink to reduce the voltage level at the load. In one embodiment, the current source is at least the inductor L1 or L11 and the current sink is ground. Additionally, if the voltage level at the load 110 or 170 is less than a minimum voltage level, the voltage control mechanism is switched to couple the current source to the load 110 or 170 and to decouple the current source from the current sink to increase the voltage level at the load. At step 215 a current control mechanism is controlled to generate the current I_(L1) or I_(L11) based on the portion of the current that is consumed by the load 110 or 170.

More illustrative information will now be set forth regarding various optional architectures and features with which the foregoing framework may or may not be implemented, per the desires of the user. It should be strongly noted that the following information is set forth for illustrative purposes and should not be construed as limiting in any manner. Any of the following features may be optionally incorporated with or without the exclusion of other features described.

FIG. 3A illustrates a current-parking switching regulator 302, within an electric power conversion system 300, in accordance with one embodiment. The upstream controller 305 is configured to generate signals coupled to the gates of the switching mechanisms M1 and M2 that enable and disable the switching mechanisms M1 and M2. When the switching mechanism M1 is enabled, the current source (i.e., inductor L1 or L11) is coupled to the electric power source 108 and when the switching mechanism M2 is disabled the current source is decoupled or isolated from the current sink. When the switching mechanism M2 is enabled, the current source is coupled to the current sink and when the switching mechanism M1 is disabled the current source is decoupled or isolated from the electric power source 108. The upstream controller 305 enables and disables the switching mechanisms M1 and M2 to generate the current I_(L1) or I_(L11).

The upstream controller 305 may be configured to perform current-mode control because the upstream controller 305 regulates the sum of the phase currents rather than a downstream voltage level when multiple voltage control mechanisms are configured to operate at different phases to regulate V_(L), as described in conjunction with FIG. 1B. While in some embodiments the upstream controller 305 can be configured to regulate absolute inductor current, I_(L1) or I_(L11), in some cases, regulating the fraction of inductor current I_(L1) or I_(L11) that is consumed by the load 110 or 170 is feasible.

The upstream controller 305 receives a signal D from the downstream controller 310. The signal D controls the operation of the voltage control mechanism and corresponds to the duty factor of the downstream controller 310. Specifically, the signal D controls the portion of current that is provided to the load 110 or 170 and therefore, corresponds to the fraction of the current I_(L1) or I_(L11) that is consumed by the load 110 or 170.

In one embodiment, the downstream controller 310 is a bang-bang control circuit that is configured to hold the voltage level at the load 110, V_(L), within a specified voltage range between a minimum voltage level (Vmin) and a maximum voltage level (Vmax). For example, when the nominal voltage level of V_(L) is 1 volt and a 20 mV ripple is specified, Vmin is specified as 0.99V and Vmax is specified as 1.01V.

The downstream controller 310 is configured to generate signals coupled to the gates of the switching mechanisms M3 and M4 that enable and disable the switching mechanisms M3 and M4. When the switching mechanism M3 is enabled, the current source (i.e., inductor L1) is coupled to the current sink (i.e., ground) and when the switching mechanism M3 is disabled the current source is decoupled or isolated from the current sink. When the switching mechanism M4 is enabled, the current source is coupled to the load 110 and when the switching mechanism M4 is disabled the current source is decoupled or isolated from the load 110.

As shown in FIG. 3A, in one embodiment the switching mechanism M3 is a N-type planar MOS transistor and the switching mechanism M4 is a P-type planar MOS transistor. The signals generated by the downstream controller 310 are configured to prevent overlap current and overvoltage on the drains of the switching mechanisms M3 and M4. Specifically, only one of the switching mechanisms M3 and M4 is enabled at a time.

The switching mechanism M3 is disabled before the switching mechanism M4 is enabled to ensure a “dead-time” when both switching mechanisms M3 and M4 are disabled. The parasitic capacitance of the drains of the switching mechanisms M3 and M4 is charged by the current I_(L1) during the dead-time and the switching mechanism M4 is enabled when the voltage across the parasitic capacitance reaches V_(L), so that current does not flow from the load 110 to the inductor L1. The dead-time between when the switching mechanism M3 is disabled and the switching mechanism M4 is enabled is controlled to allow the inductor L1 to charge the drain of the switching mechanism M4 to V_(L) before the switching mechanism M4 is enabled. The dead-time also ensures that switching mechanism M3 is disabled when the switching mechanism M4 is enabled to avoid shoot-through current from the load 110 through the switching mechanisms M4 and M3 to ground.

Similarly the dead-time between when the switching mechanism M4 is disabled and the switching mechanism M3 is enabled is controlled to keep the drain of the switching mechanism M4 from being charged too high by I_(L1) before the switching mechanism M3 is enabled. The dead-time between when the switching mechanism M4 is disabled and the switching mechanism M3 is enabled also ensures that switching mechanism M4 is disabled when the switching mechanism M3 is enabled to avoid shoot-through current from the load 110 through the switching mechanisms M4 and M3 to ground.

When power is initially applied to the electric power conversion system 300, V_(L) is zero and many nanoseconds are needed to charge the capacitor C1 to a voltage between Vmin and Vmax. The downstream controller 310 may be configured to operate using an auxiliary supply voltage V_(ST) that is turned on at startup, before the upstream controller 305 begins to generate the current I_(L1). The switching mechanism M4 is enabled to charge C1 when the current source starts up. In one embodiment, the auxiliary supply voltage is not used for the downstream controller 310 and the downstream controller 310 is configured to disable the switching mechanism M3 and enable the switching mechanism M4 until V_(L) reaches Vmax.

FIG. 3B illustrates waveforms of the first and second signals that control the portion of inductor current I_(L1) that is provided to the load 110 of the current-parking switching regulator 302 shown in FIG. 3A, in accordance with one embodiment. In one embodiment, the non-overlapping enable signals comprise a first signal and a second signal. The first signal controls (i.e., enables and disables) the switching mechanism M4 and the second signal controls the switching mechanism M3. When the switching mechanism M4 is a P-type MOS transistor, an inverted version of the first signal is coupled to the gate of the P-type MOS transistor. For the purposes of understanding the waveforms 315 shown in FIG. 3B, the inverted first signal is shown. When the inverted version of the first signal is high the switching mechanism M4 is enabled and when the inverted version of the first signal is low, the switching mechanism M4 is disabled. Similarly, when the second signal is high the switching mechanism M3 is enabled and when the second signal is low, the switching mechanism M3 is disabled.

Separate delays may be used for a first signal that enables the switching mechanism M3 and a second signal the enables the switching mechanism M4. Furthermore, a different delay may be used for a rising transition than is used for a falling transition of the first and/or the second signal. The delays control the duration of the dead-times when both switching mechanisms M3 and M4 are disabled (i.e., when the inverted first signal and the second signal are negated) and the current source is decoupled from the load and decoupled from the current sink. The duration of an “enabling” dead-time between when the switching mechanism M3 is disabled and the switching mechanism M4 is enabled may differ from the duration of a “disabling” dead-time between when the switching mechanism M4 is disabled and the switching mechanism M3 is enabled.

The “disabling” dead-time occurs between when the switching mechanism M4 is disabled by the first signal and the switching mechanism M3 is enabled by the second signal. The “enabling” dead-time occurs between when the switching mechanism M3 is disabled by the second signal and the switching mechanism M4 is enabled by the first signal. During the disabling and the enabling dead-times the switching mechanisms M3 and M4 are disabled (i.e., when the inverted first signal and the second signal are negated). Therefore, the current source is decoupled from both the current sink and the load. The enabling dead-time may be longer than the disabling dead-time to charge the parasitic capacitance at the drains of the switching mechanisms M3 and M4 between the current source and the voltage control mechanism by the current I_(L1). When the switching mechanism M4 is an N-type MOS transistor, an inverted version of the first signal is coupled to the gate of the switching mechanism M4.

As previously explained in conjunction with FIG. 3A, the upstream controller 305 may be configured to control the current control mechanisms based on the fraction of inductor current I_(L1) that is consumed by the load 110 which corresponds to the duty factor of the signal D generated by the downstream controller 310. Therefore, the signal D is provided as an input to the upstream controller 305. The upstream controller 305 may include a duty factor measurement unit that is configured to measure the duty factor using the signal D. In one embodiment, the downstream controller 310 is configured to generate the duty factor for output to the upstream controller 305.

FIG. 3C illustrates a duty factor measurement unit 320, in accordance with one embodiment. The duty factor measurement unit 320 is configured to measure the duty factor by low-pass filtering the D signal. A one-pole low-pass filter comprising a resistor R and a capacitor C generates DA, an analog version of the duty factor signal D. A digital version of the downstream duty factor (DDF) is generated by converting DA to a digital signal using an analog-to-digital converter 322. Typically, the downstream controller 310 operates at a frequency of hundreds of MHz and the upstream controller 305 operates at a frequency of hundreds of kHz, therefore a single pole filter with a pole at 1 MHz is sufficient to measure the duty factor of D.

FIG. 3D illustrates another duty factor measurement unit 325 of the upstream controller 305, in accordance with one embodiment. The duty factor measurement unit 325 is configured to measure the duty factor by passing the signal D through a tapped delay line and an array of flip-flops 330 clocked by D are configured to sample the output of each delay element. A duty factor calculator 335 processes the outputs of the flip-flops 330 to determine the number of taps to last falling edge of the signal D and the number of taps to the last rising edge of the signal D. The duty factor is then calculated from these two measurements as DDF=(R−F)/R, where F is the number of taps to the last falling edge and R is the number of taps to the last rising edge. At very high duty factors, the period of D may be large enough that the last rising edge cannot be identified by the duty factor calculator 335, in which case, the duty factor calculator 335 may set DDF to a maximum value. At very low load currents, the switching frequency of the downstream controller 310 may be low enough that neither the rising nor the falling edge of D is identified by the duty factor calculator 335, in which case, the duty factor calculator 335 may set DDF to a minimum value.

FIG. 4A illustrates the upstream controller 305 of the current-parking switching regulator 302 shown in FIG. 3A, in accordance with one embodiment. The upstream controller 305 may be configured to provide a reserve amount of current I_(L1) that is greater than the current that is consumed by the load 110. For example, a 20% reserve may be provided by maintaining I_(L1) at a target current of 10 amps assuming that the current consumed by the load 110 is 8 amps. A target duty factor is specified that corresponds to the target current. DDF (i.e., the measured downstream duty factor of the signal D) increases in response to higher current demands by the load 110, and, when DDF is higher than the target duty factor, I_(L1) is increased to provide current to the load 110 using a lower duty factor at the downstream controller 310 (i.e., a duty factor that is closer to the target duty factor). Similarly, DDF decreases in response to lower current demands by the load 110, and when DDF is lower than the target duty factor, I_(L1) is decreased to provide current to the load 110 using a duty factor that is closer to the target duty factor.

The duty factor measurement unit 420 measures the duty factor of the signal D and may be implemented as the duty factor measurement unit 320 or 325. The upstream controller 305 is configured as a PWM controller configured to maintain DDF above the target duty factor that is specified by a duty-factor command (DFC). DFC should be low enough that DDF remains in a target range over an entire period of the upstream controller 305 (i.e., the period of the PWM frequency).

In one embodiment, the target duty factor varies based on a processing workload associated with the load 110. For example, just before a heavy workload is initiated, the target duty factor is decreased to increase the current. When a target current is used to control generation of the current, the target current may be increased just before a heavy workload is initiated.

A set-reset flip-flop 415 is set by an oscillator 425 at the PWM frequency (typically 300 kHz) and reset by a comparator 410 that indicates when the DDF falls below DFC. The Q output of the flip-flop 415 drives a current control unit 405 that generates enable signals for the switching mechanisms M1 and M2 of the current control mechanism. In one embodiment, the current control unit 405 is a half-bridge driver. The Q output is high when the R input is low and the output of the oscillator 425 is high. The Q output will remain high until the R input is high. The Q output is low whenever the R input is high (when DDF falls below DFC). The current control unit 405 enables the switching mechanism M1 and disables the switching mechanism M2 when Q is high to increase the current I_(L1). The current control unit 405 disables the switching mechanism M1 and enables the switching mechanism M2 when Q is low to decrease the current I_(L1). The enable signals generated by the current control unit 405 should be non-overlapping so that the output of the electric power source 108 is not shorted to ground. The enable signal provided to the switching mechanism M1 may be configured to implement a bootstrap power supply to generate a gate drive above the voltage at the electric power source 108 (e.g., 12V).

FIG. 4B illustrates another version of the upstream controller 305 of the current-parking switching regulator 302, in accordance with one embodiment. A current measurement unit 422 is configured to divide the portion of the current that is provided to the load 110, current I_(Load), by DDF to compute the current I_(L1). A comparator 412 is configured to compare the computed current to a target current specified by a current command (CC). Reset goes high when the computed current is greater than the target current to reduce the generated current I_(L1).

In another embodiment, the current measurement unit 422 may be configured to measure I_(L1) directly and the duty factor measurement unit 420 is omitted. The comparator 412 would be configured to compare the measured I_(L1) to a target current specified by the current command. Reset would go high when the measured current I_(L1) is greater than the target current to reduce the generated current I_(L1).

FIG. 4C illustrates a flowchart 440 of a method for an upstream controller 305 to control the current generated by a current control mechanism, in accordance with one embodiment. At step 205, a current source is configured by the upstream controller 305 to generate a current I_(L1). At step 210, a voltage control mechanism is configured by the downstream controller 310 to provide a portion of the current to the load 110 to regulate the voltage level at the load 110. At step 407, the duty factor measurement unit 420 measures the duty factor of the signal D that controls the portion of the current that is provided to the load 110. The duty factor measurement unit 420 produces the output DDF. At step 430, the upstream controller 305 determines if the generated current I_(L1) should be reduced, and, if not, at step 435, the upstream controller 305 configures the current control mechanism to increase the current I_(L1). Otherwise, at step 442, the upstream controller 305 configures the current control mechanism to decrease the generated current I_(L1).

In one embodiment, the measured duty factor is compared with a target duty factor to generate the enable signals for the current control mechanism. The measured duty factor (DDF) corresponds to the portion of the current that is provided to the load 110 (I_(Load)). In another embodiment, I_(Load) is measured and combined with DDF to produce a computed current that is compared with a target current to generate the enable signals for the current control mechanism. In each of these embodiments, generation of the current I_(L1) is based on the portion of the current that is provided to the load 110. In yet another embodiment, the current I_(L1) is measured and compared with a target current to generate the enable signals for the current control mechanism.

FIG. 5A illustrates another flowchart 500 of a method for regulating the voltage level provided to the load 110 or 170 using the downstream controller 310 or 360 (or the controller 105 or 165 that includes a downstream controller), in accordance with one embodiment. At step 502, the switching mechanisms in the voltage control mechanism are initialized. Specifically, the switching mechanism M3 is disabled and the switching mechanism M4 is enabled. In another embodiment, the auxiliary supply voltage V_(ST) is provided to the downstream controller, and step 502 is replaced with a step that provides the auxiliary supply to the downstream controller before the electric power 108 source provides a supply voltage to the current source.

At step 505, the upstream controller 305 (or controller 105 or 165) configures the current control mechanism to generate the current I_(L1) through the inductor L1. The current control mechanism may be configured to provide a current that is greater than an average current needed by the load 110 or 170. At step 510, the downstream controller configures the voltage control mechanism to provide a portion of the current to the load 110 or 170 to regulate the voltage level, V_(L) at the load 110. At step 515, the downstream controller determines if V_(L) is greater than Vmax, and, if so, then at step 525, the voltage control mechanism is switched to decouple the current source from the load 110 or 170 and to couple the current source (i.e., the inductor L1) to a current sink (i.e., ground) to provide a lesser portion of I_(L1) to the load 110 or 170 to reduce V_(L). After step 525, the downstream controller returns to step 515.

If, at step 515, V_(L) is not greater than Vmax, then at step 530, the downstream controller determines if V_(L) is less than Vmin. If V_(L) is less than Vmin, then at step 535 the downstream controller configures the voltage control mechanism to couple the current source to the load 110 or 170 and to decouple the current source from the current sink to provide a greater portion of I_(L1) to the load 110 or 170 to increase V_(L). After step 535, the downstream controller returns to step 515. Otherwise, when V_(L) is not greater than Vmax and is not less than Vmin (i.e., V_(L) is within the range bounded by Vmin and Vmax), then the downstream controller returns to step 515.

The portion of the current that is provided to the load 110 or 170 is determined by the signal D that is generated by the downstream controller 310 or 360. The signal D that alternately enables the first switching mechanism M4 allowing a portion of the current to flow to the load 110 or 170 while disabling a second switching mechanism M3 and then enables the second switching mechanism to pull the inductor L1 (or L2 for the electric power conversion device 180) to ground while disabling the second switching mechanism to isolate the load 110 or 170 from the inductor. In response to a current transient, the downstream controller 310 or 360 quickly increases or decreases the portion of the current that is provided to the load 110 or 170 and maintains the voltage level V_(L) within a predetermined range bounded by Vmin and Vmax. Specifically, when V_(L) is greater than Vmax, D goes low to divert current away from load 170 and when V_(L) is less than Vmin, D goes high to source current to the load 170.

FIG. 5B illustrates a system 550 including a current-parking switching regulator driving two loads, loads 110-A and 110-B, with independently controller voltages V_(LA) and V_(LB) using a shared current source, according to one embodiment. As shown in FIG. 5B, the single inductor L1 provides the current I_(L1), a portion of which is provided to each of the two loads 110-A and 110-B. In one embodiment, the portions of the current I_(L1) are not provided to the two loads 110-A and 110-B simultaneously. A filter capacitor CIA is coupled to the load 110-A and a filter capacitor C1B is coupled to the load 110-B. A separate downstream controller 510-A and 510-B and respective switching mechanism M4A and M4B is associated with each of the loads. However, the switching mechanism M3 may be shared by the downstream controllers 510-A and 510-B. The downstream controllers 510-A and 510-B may each be one of the downstream controllers 310 or 360.

The D output signals, DA and DB that are generated by the downstream controllers 510-A and 510-B are combined to give operating priority to the load 110-A. In one embodiment, load 110-A is the most critical or highest-current load. When DA is high, the switching mechanism M4A is enabled, coupling the current source to the load 110-A and the switching mechanisms M4B and M3 are both disabled. When the switching mechanism M4A is enabled the current I_(L1) is provided to capacitor CIA and V_(LA) ramps up while V_(LB) ramps down. When DA is low DB may be high, enabling the switching mechanism M4B and disabling the switching mechanisms M4A and M3. When the switching mechanism M4B is enabled current I_(L1) is provided to capacitor C1B and V_(LB) ramps up while V_(LA) ramps down. When DA and DB are both low, the switching mechanism M3 is enabled and both switching mechanisms M4A and M4B are disabled causing the current I_(L1) to be “parked” in the inductor L1 while both V_(LA) and V_(LB) ramp down. The effective duty factor of the system 550 is the duty factor of the signal formed by the logical “OR” of DA and DB, shown in FIG. 5B as the signal D.

FIG. 5C illustrates a system 560 including a current-parking switching regulator, according to one embodiment. The current-parking switching regulator in the system 560 may be one of the electric power conversion devices 120 and 180 shown in FIGS. 1A and 1C, respectively, or one of the current-parking switching regulators shown in FIGS. 3A, 3C, and 4A.

The electric power source 108 is coupled to the current control mechanism and the voltage control mechanism of the current-parking switching regulator with the inductor L1. In an alternate embodiment, the electric power source 108 is coupled to the current control mechanism and the voltage control mechanism of the current-parking switching regulator with the inductors L11 and L2. The upstream controller 305 is configured to generate a current through the inductor L1. The downstream controller 510 may be one of the downstream controllers 310 or 360 and is configured to regulate the voltage level at the load, i.e., circuit 580. In one embodiment, the downstream controller 510 is configured to maintain the voltage level at the circuit 580 within a predetermined range bounded by Vmin and Vmax.

The inductor L1 is positioned outside of a package 570 that encloses the circuit 580. A second inductor L2 (not shown) may be positioned inside of the package 570, reducing the second parasitic capacitance CPB compared with the first parasitic capacitance CPA, as described in conjunction with FIG. 1C. The second inductor L2, the switching mechanisms M3 and M4 (or M13 and M14), and the capacitor C1 (or C11) may be fabricated as part of the die 575 that includes the circuit 580. In one embodiment, the second inductor L2 a planar air-core inductor and the switching mechanisms M3 and M4 (or M13 and M14) are planar MOS transistors. Although a single phase of the current-parking switching regulator with a split inductor is shown in FIG. 5B, multiple phases of the current-parking switching regulator with a split inductor or a combination of one or more current-parking switching regulators (with or without a split inductor) may be used with one or more conventional electric power conversion devices to provide power to the circuit 580.

FIG. 6A illustrates waveforms 600 generated by the current-parking switching regulator 302, in accordance with one embodiment. The upstream controller is a PWM controller that maintains the duty factor of the signal D below a target duty factor (as shown in FIG. 4A) or that maintains the current above a target current (as shown in FIG. 4B). The downstream controller may be a bang-bang controller that is configured to maintain V_(L) within a range bounded by Vmin and Vmax.

The top trace is the duty factor (DF) of the signal D that increases as the current I_(L1) (third trace) decreases to provide constant current to the load. The second trace is the first signal of the enable control signals generated by the upstream controller 305 that is coupled to the switching mechanism M1 (M1 gate). When M1 gate is high the current I_(L1) through the inductor L1 ramps up steeply as the upstream side of the inductor L1 is connected to the (12V) electric power source 108. When M1 gate is low, the current I_(L1) slowly decays as the upstream side of the inductor L1 is connected to GND through the switching mechanism M2.

In the simulation producing the waveforms 600 there is a current transient in the load current I_(Load) from 20 A to 23 A at 5 μs and a step change in the target duty factor from 0.7 to 0.77 at 12 μs. FIG. 6B illustrates an enlarged view of a portion of the waveforms 600 shown in FIG. 6A, in accordance with one embodiment.

As shown in both FIG. 6A and the zoomed plot of FIG. 6B, the current transient results in a step increase in the duty factor DF and a step decrease in the operating frequency of the downstream controller 310 (implemented as a bang-bang controller), but the voltage V_(L) remains in the range bounded by Vmin and Vmax. As shown in the FIG. 6B, the downstream controller 310 responds immediately to the current transient by increasing duty factor DF so that V_(L) remains within the target voltage range. FIG. 6B also illustrates how the frequency of the downstream controller 310 is reduced at the higher duty factor because the rising slope of V_(L) is decreased.

FIG. 6C illustrates another enlarged view of a portion of the waveforms 600 shown in FIG. 6A, in accordance with one embodiment. FIG. 6C illustrates how duty factor and the operating frequency of the downstream controller 310 vary during the long upswing in the current I_(L1) from 6.67 μs to 7 μs. At the start of the ramp of the current I_(L1), the duty factor is very high, over 0.9, and the operating frequency of the downstream controller 310 is correspondingly low. As the current I_(L1) ramps up, the duty factor ramps down and the operating frequency of the downstream controller 310 increases.

FIG. 7 illustrates an exemplary system 700 in which the various architecture and/or functionality of the various previous embodiments may be implemented. As shown, a system 700 is provided including at least one central processor 701 that is connected to a communication bus 702. The communication bus 702 may be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect), PCI-Express, AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol(s). The system 700 also includes a main memory 704. Control logic (software) and data are stored in the main memory 704 which may take the form of random access memory (RAM).

The system 700 also includes input devices 712, a graphics processor 706, and a display 708, i.e. a conventional CRT (cathode ray tube), LCD (liquid crystal display), LED (light emitting diode), plasma display or the like. User input may be received from the input devices 712, e.g., keyboard, mouse, touchpad, microphone, and the like. In one embodiment, the graphics processor 706 may include a plurality of shader modules, a rasterization module, etc. Each of the foregoing modules may even be situated on a single semiconductor platform to form a graphics processing unit (GPU).

In the present description, a single semiconductor platform may refer to a sole unitary semiconductor-based integrated circuit or chip. It should be noted that the term single semiconductor platform may also refer to multi-chip modules with increased connectivity which simulate on-chip operation, and make substantial improvements over utilizing a conventional central processing unit (CPU) and bus implementation. Of course, the various modules may also be situated separately or in various combinations of semiconductor platforms per the desires of the user. One or more of the systems 550 and 500 shown in FIGS. 5A and 5B, respectively, may be incorporated in the system 700 to provide power to one or more of the chips.

The system 700 may also include a secondary storage 710. The secondary storage 710 includes, for example, a hard disk drive and/or a removable storage drive, representing a floppy disk drive, a magnetic tape drive, a compact disk drive, digital versatile disk (DVD) drive, recording device, universal serial bus (USB) flash memory. The removable storage drive reads from and/or writes to a removable storage unit in a well-known manner. Computer programs, or computer control logic algorithms, may be stored in the main memory 704 and/or the secondary storage 710. Such computer programs, when executed, enable the system 700 to perform various functions. The main memory 704, the storage 710, and/or any other storage are possible examples of computer-readable media.

In one embodiment, the architecture and/or functionality of the various previous figures may be implemented in the context of the central processor 701, the graphics processor 706, an integrated circuit (not shown) that is capable of at least a portion of the capabilities of both the central processor 701 and the graphics processor 706, a chipset (i.e., a group of integrated circuits designed to work and sold as a unit for performing related functions, etc.), and/or any other integrated circuit for that matter.

Still yet, the architecture and/or functionality of the various previous figures may be implemented in the context of a general computer system, a circuit board system, a game console system dedicated for entertainment purposes, an application-specific system, and/or any other desired system. For example, the system 700 may take the form of a desktop computer, laptop computer, server, workstation, game consoles, embedded system, and/or any other type of logic. Still yet, the system 700 may take the form of various other devices including, but not limited to a personal digital assistant (PDA) device, a mobile phone device, a television, etc.

Further, while not shown, the system 700 may be coupled to a network (e.g., a telecommunications network, local area network (LAN), wireless network, wide area network (WAN) such as the Internet, peer-to-peer network, cable network, or the like) for communication purposes.

While various embodiments have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of a preferred embodiment should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. 

What is claimed is:
 1. A method, comprising: configuring a current source to provide a current to a voltage control mechanism; configuring the voltage control mechanism to provide a portion of the current to a load through a first switching mechanism that is directly coupled between the current source and the load and controlled by a first signal, wherein the portion of the current increases as a duty factor of the first signal increases and the portion of the current decreases as the duty factor of the first signal decreases; measuring the duty factor of the first signal to produce a measured duty factor; comparing the measured duty factor with a target duty factor corresponding to a current consumed by the load to produce a comparison output; and generating, based on the comparison output, a second signal to control a second switching mechanism within the current source to adjust the current based on the comparison result.
 2. The method of claim 1, wherein the second signal couples and decouples the current source to an electric power source to adjust the current.
 3. The method of claim 1, wherein the second signal couples and decouples the current source to a current sink to adjust the current.
 4. The method of claim 1, further comprising decreasing the current that is generated when the measured duty factor is less than the target duty factor.
 5. The method of claim 1, wherein the target duty factor varies according to a processing workload associated with the load.
 6. The method of claim 1, wherein the measuring comprises filtering the first signal to produce the measured duty factor.
 7. The method of claim 1, wherein the measuring comprises sampling a tapped delay line to produce the measured duty factor.
 8. The method of claim 1, further comprising increasing the current when the measured duty factor is greater than the target duty factor.
 9. The method of claim 1, wherein the current is greater than an average current that is needed to regulate an output voltage level at the load.
 10. The method of claim 1, wherein the voltage control mechanism comprises an n-type switching mechanism that operates at lower voltages than an n-type switching mechanism within the current source.
 11. The method of claim 1, wherein the second switching mechanism is coupled to an electric power source providing a voltage level that is greater than an output voltage level at the load.
 12. The method of claim 1, wherein the first signal operates at a first frequency and the second signal operates at a second frequency that is substantially lower than the first frequency.
 13. The method of claim 1, wherein the measured duty factor is a digital signal.
 14. A method, comprising: configuring a current source to provide a current to a voltage control mechanism; configuring the voltage control mechanism to provide a portion of the current to a load through a first switching mechanism that is directly coupled between an output of the current source and the load and controlled by a first signal, wherein the first signal maintains an output voltage level at the load within a predetermined range bounded by a minimum voltage and a maximum voltage; measuring the current at the output of the current source to produce a measured current; comparing the measured current to a target current corresponding to a current consumed by the load to produce a comparison output; and generating, based on the comparison output, a second signal to control a second switching mechanism within the current source to adjust the current based on the comparison result.
 15. The method of claim 14, wherein the second signal controls the second switching mechanism to increase the current when the measured current is not greater than the target current.
 16. The method of claim 14, wherein the generating of the current comprises: coupling the current source to an electric power source according to a fixed frequency when the measured current is not greater than the target current; and decoupling the current source from the electric power source when the measured current is greater than the target current.
 17. The method of claim 14, wherein the second switching mechanism is coupled to an electric power source providing a voltage level that is greater than the output voltage level at the load.
 18. An electric power conversion device, comprising: a current source configured to generate a current; a voltage control mechanism configured to provide a portion of the current to a load through a first switching mechanism that is directly coupled between the current source and the load and controlled by a first signal; and an upstream controller that is coupled to the current source and is configured to: measure a duty factor of the first signal to produce a measured duty factor, wherein the portion of the current increases as the duty factor of the first signal increases and the portion of the current decreases as the duty factor of the first signal decreases; compare the measured duty factor with a target duty factor corresponding to a current consumed by the load to produce a comparison output; and generate, based on the comparison output, a second signal to control a second switching mechanism within the current source to adjust the current based on the comparison result.
 19. The electric power conversion device of claim 18, wherein the second switching mechanism is coupled to an electric power source providing a voltage level that is greater than an output voltage level at the load.
 20. An electric power conversion device, comprising: a current source configured to generate a current; a voltage control mechanism configured to provide a portion of the current to a load through a first switching mechanism that is directly coupled between an output of the current source and the load and controlled by a first signal, wherein the first signal maintains an output voltage level at the load within a predetermined range bounded by a minimum voltage and a maximum voltage; and an upstream controller that is coupled to the current source and is configured to: measure the current at the output of the current source to produce a measured current; compare the measured current to a target current corresponding to a current consumed by the load to produce a comparison output; and generate, based on the comparison output, a second signal to control a second switching mechanism within the current source to adjust the current based on the comparison result.
 21. The electric power conversion device of claim 20, wherein the upstream controller is further configured to generate the second signal to increase the current when the measured current is not greater than the target current.
 22. The electric power conversion device of claim 20, wherein the upstream controller is further configured to: couple the current source to an electric power source according to a fixed frequency when the measured current is not greater than a target current; and decouple the current source from the electric power source when the measured current is greater than the target current.
 23. The electric power conversion device of claim 20, wherein the second switching mechanism is coupled to an electric power source providing a voltage level that is greater than the output voltage level at the load. 